All-Digital RF Phase-Locked Loops Exploiting Phase Prediction
نویسندگان
چکیده
منابع مشابه
All-Digital RF Phase-Locked Loops Exploiting Phase Prediction
This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the pha...
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partial fulfillment of the requirements for the award of Bachelor of Technology (Honours) in 2009, is an authentic record of the work carried out by Sushil Subramanian under my guidance and supervision. In my opinion, this work fulfills the requirement for which it has been submitted. This thesis has not been submitted to any other university or institution for any degree or diploma.
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Over the past decade, Phase-Locked Loops (PLLs) have become an integral part of the modern ASIC design. PLLs provide the clocks that sequence the operation of the various blocks on an ASIC chip as well as synthesize their communications. There are various types of PLLs targeting specific applications. Clock generator PLLs are capable of large frequency multiplication. They are primarily used to...
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An optimal algorithm is presented for tracking the phase of a slowly modulating signal by means of digital sampling of its sign. Error bounds and a numerical illustration are given.
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ژورنال
عنوان ژورنال: IPSJ Transactions on System LSI Design Methodology
سال: 2014
ISSN: 1882-6687
DOI: 10.2197/ipsjtsldm.7.2